1. Field of the Invention
The present invention relates to circuit for sensing the state of matrix cells in MOS EPROM memories including an offset current generator.
2. Prior Art
Essentially two kinds of circuits for sensing the content of EPROM memory cells are known:
(a) the unbalanced-load type;
(b) the type with current offset towards the ground.
In unbalanced-load circuits, the load on the reference cell is typically twice that of the matrix cells. This type of circuit can operate with very low values of the supply voltage V.sub.cc, which in practice coincides with the threshold voltage of the virgin cell, but its maximum voltage is limited, since it is determined by the crossing between the characteristic curve of the written cell and that of the reference cell. The performance of the circuit is therefore limited as the supply voltage varies upwards.
In order to solve this problem, circuits with a current offset towards the ground have been introduced, wherein the characteristic curves of the reference cell, of the virgin cell and of the written cell are parallel. However this type of circuit, too, has new disadvantages, i.e.: the value of the minimum V.sub.cc is satisfactory for the virgin cell, but for the written cell it is determined by the crossing between the characteristic curve of the reference cell and that of the written cell, and is higher than in unbalanced-load circuits.
Besides the above described problem, which is of a static nature, the circuit with current offset towards the ground also has a dynamic disadvantage. In fact, while during the reading of a virgin cell the current in the branch of the matrix cell always absorbs a higher current than the reference side, and therefore their difference can be sensed immediately, in the case of a written cell the currents in the two branches are initially identical, since the written cell in any case absorbs a current equal to the offset current, and said current starts to be greater than the offset current only after a certain period of delay. This wait time constitutes a delay which extends the total access time of the device during a read operation.
A current offset circuit is described, by way of example, in the antedated Italian patent application No. 21682-A/86 filed on Sept. 12, 1986, and entitled "Circuito di rilevamento dello stato di celle di matrice in memorie EPROM in tecnologia MOS", to which reference is made for a detailed description of its operation and for a general discussion of the problems of sensing EPROM memory cells and unbalanced-load circuits.